Accomplished Engineer with a track record at ZTE Corporation, specializing in modem chip design and digital front-end development. Expert in Verilog and proficient in Python, I led the design of a critical Package Filter module, enhancing performance through innovative features. Collaborates effectively across teams, demonstrating strong problem-solving skills and a deep understanding of the IC design process.
Positive and collaborative, with strong aptitude for problem-solving and project management. Knowledge of engineering principles and project planning, coupled with proficiency in AutoCAD and MS Project. Committed to delivering innovative solutions and driving project success.
Independently led the design of the self-developed Modem chip's Package Filter module, including troubleshooting validation issues and developing new features.My responsibilities included not only the initial design and architecture but also troubleshooting and resolving validation issues encountered during the testing phase. I actively contributed to enhancing the module’s performance by developing new features, optimizing its functionality, and ensuring it met the required specifications. Additionally, I collaborated with cross-functional teams to ensure seamless integration with other chip components and supported the overall testing and debugging process throughout the project lifecycle.
Worked on the self-developed DPU chip's Virtio-Queue-Manager module, assisting Mentor in the module design. Responsibilities included bug detection, validation issue resolution, and participation in the entire process from front-end design to post-tapeout screening.
Be proficient in Verilog language programming
Understand knowledge and process of chip design
Familiar with the use of Linux workstations
Familiar with shell, Python and other scripting skills
Familiar with TCP/IP protocol, network/communication basics
Familiar with IC design process, understand low power consumption, area, static timing analysis, etc